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CPUを作ろう ~計算機教材とマイコンと電子工作~

K-COM(Verilog)の作成


VerilogによるK-COMの設計

ソースのみあげておきます.設計方針はAHDLによるものとほぼ同じです.
階層化して記述しています.最後のkcomがトップモジュールです.


クロックジェネレータ

module clock(reset, gclk, tclk, sclk );
input reset, gclk;
output tclk, sclk;
reg tclk, sclk;

always @(posedge gclk or posedge reset) begin
if (reset) sclk <= 1'b0;
else sclk <= ~sclk;
end
always @(negedge gclk or posedge reset) begin
if (reset) tclk <= 1'b0;
else tclk <= ~tclk;
end
endmodule


プログラムカウンタおよび命令レジスタ

module pcir(reset, tclk, halt, pc, ir, a_bus, d_bus, select);
input reset, tclk;
input [7:0] d_bus, select;
output halt;
output [4:0] a_bus;
output [4:0] pc;
output [7:0] ir;
reg [4:0] pc;
reg [7:0] ir;

always @(posedge tclk or posedge reset) begin
if (reset) begin pc<=5'b0; ir<=8'b0; end
else begin
if(select[7]) pc<=ir[4:0];
else if(select[4]) pc<=pc+5'b1;
else if(select[3]) ir<=d_bus;
end
end
assign a_bus = (select[0])? pc: ir[4:0];
assign halt = (ir==8'hff);

endmodule


ALUおよびアキュームレータ

module alu(reset, tclk, ir, select, acc, latch, c, z, d_bus);
input reset, tclk;
input [7:0] select,ir;
output [7:0] acc, latch;
reg [7:0] acc, latch;
output z,c;
reg c,z;
inout [7:0] d_bus;

always @(posedge tclk or posedge reset) begin
if (reset) begin acc<=8'b0; latch<=8'b0; c<=1'b0; z<=1'b0; end
else begin
if(select[5]) begin
casex(ir[7:5])
3'b000: begin {c,latch}<=acc + d_bus; z<=((acc + d_bus)==8'b0); end
3'b001: begin {c,latch}<=acc - d_bus; z<=((acc - d_bus)==8'b0); end
3'b010: begin {c,latch}<=~(acc & d_bus); z<=((~(acc & d_bus))==8'b0); end
3'b011: begin {c,latch}<=acc << 1; z<=((acc <<1 )==8'b0); end
3'b101: latch<=acc;
endcase
end
if(select[6]) acc<=d_bus;
end
end
assign d_bus= (select[1])? latch: 8'bz;

endmodule


メモリおよびI/Oポート

module mem(tclk, a_bus, inp, oup, select, d_bus);
input tclk;
input [4:0] a_bus;
input [7:0] inp;
input [7:0] select;
output [7:0] oup;
inout [7:0] d_bus;
reg [7:0] mem[0:31];
reg [7:0] oup;

function [7:0] memout; // memory read
input [4:0] a_bus;
case(a_bus)
0:memout =8'h9e;
1:memout =8'hbf;
2:memout =8'h44;
3:memout =8'he0;
4:memout =8'h00;
30:memout =inp;
default: memout =mem[a_bus];
endcase
endfunction

always @(posedge tclk) begin
if(select[2])
if (a_bus==31) oup<=d_bus; else mem[a_bus] <=d_bus;
end
assign d_bus = (~select[1])? memout(a_bus): 8'bz;

endmodule


コントローラ

module control(reset, sclk, ir, c, z, select);
input reset, sclk, c, z;
input [7:0] ir;
output [7:0] select;
reg [1:0] ss;
reg [7:0] select;

// Control signal
// select[7]: PC load
// select[6]: ACC latch
// select[5]: ALU, c,z latch
// select[4]: PC count up or load enable
// select[3]: IR latch
// select[2]: memory read/write
// select[1]: ACC data from ALU:1 or memory:0
// select[0]: address select PC:1 or IR_L:0

always @(posedge sclk or posedge reset) begin
if (reset) ss<=2'b00;
else case (ss)
2'b00: begin select<=8'b00001001; ss<=2'b01; end // fetch cycle 1
2'b01: begin select<=8'b00010000; ss<=2'b10; end // fetch cycle 2
2'b10: // exec cycle 1
casex (ir[7:5])
3'b0XX: begin select<=8'b00100000; ss<=2'b11; end // ADD,SUB,NAND,SHIFT
3'b100: begin select<=8'b01000000; ss<=2'b00; end // LD
3'b101: begin select<=8'b00100000; ss<=2'b11; end // ST
3'b110: begin // JPC
if(~c) begin select<=8'b00000000; ss<=2'b00; end // C=0, nop
if(c) begin select<=8'b10000000; ss<=2'b00; end // C=1, jump
end
3'b111: begin // JPNZ
if(~z) begin select<=8'b10000000; ss<=2'b00; end // Z=0, jump
if(z) begin select<=8'b00000000; ss<=2'b00; end // z=1, nop
end
endcase
2'b11: // exec cycle 2
casex (ir[7:5])
3'b0XX: begin select<=8'b01000010; ss<=2'b00; end // ADD,SUB,NAND,SHIFT
3'b101: begin select<=8'b00000110; ss<=2'b00; end // ST
endcase
endcase
end

endmodule


K-COMのトップモジュール

module kcom(reset,clk,tclk,sclk,a_bus,pc,d_bus,ir,acc,latch,c,z,select,inp,oup,halt);
input reset, clk;
input [7:0] inp;
output tclk, sclk, c, z, halt;
output [4:0] a_bus, pc;
output [7:0] d_bus, ir, acc, latch, select, oup;
wire gclk;

assign gclk= clk & ~halt;
clock clock(reset, gclk, tclk, sclk);
pcir pcir(reset, tclk, halt, pc, ir, a_bus, d_bus, select);
alu alu(reset, tclk, ir, select, acc, latch, c, z, d_bus);
mem mem(tclk, a_bus, inp, oup, select, d_bus);
control control(reset, sclk, ir, c, z, select);

endmodule



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